What is the difference between wire and reg in Verilog?

In Verilog, wire and reg are fundamental data types with distinct characteristics:

Wire

Represents a physical connection: Think of it as a simple wire connecting two points in a circuit.
No storage capability: A wire cannot store a value on its own. It simply transmits the value it receives from its source.
Driven by continuous assignments: wires are typically driven by continuous assignments (assign) or as outputs of modules.

Reg

Represents a storage element: A reg can hold a value and retain it until a new value is assigned.
Used within procedural blocks: regs are primarily used within procedural blocks (like always blocks) to model registers, flip-flops, and other memory elements.
Can be used for both combinational and sequential logic: While often associated with sequential logic, reg can also be used for combinational logic within procedural blocks.

// Wire declaration
wire a, b, c; 
assign c = a & b; 

// Reg declaration
reg d; 
always @ (posedge clk) begin
    d <= a | b; 
end

In this example :

a, b, and c are declared as wires. The assign statement defines a continuous assignment, meaning the value of c is always updated based on the values of a and b.
d is declared as a reg. The always block defines a sequential assignment, meaning the value of d is updated only on the rising edge of the clock signal (posedge clk).

By understanding the distinctions between wire and reg, you can effectively model various hardware components and behaviors in Verilog.