What are blocking and non-blocking assignments in Verilog?

In Verilog, blocking and non-blocking assignments are two distinct ways to assign values to variables within procedural blocks (like always blocks). They have significant implications for how your Verilog code simulates and synthesizes.

Blocking Assignment (=)

Sequential Execution: Blocking assignments are executed sequentially, one after another.
Immediate Update: The value on the right-hand side of the assignment is immediately assigned to the variable on the left-hand side.
Example :

reg a, b, c; 

always @ (posedge clk) begin
  a = 1; // Assign 1 to a
  b = a; // Assign the current value of a (which is now 1) to b
  c = b; // Assign the current value of b (which is 1) to c
end

In this example, a is assigned 1 first. Then, b is assigned the current value of a, which is 1. Finally, c is assigned the current value of b, which is also 1.

Non-Blocking Assignment (<=)

Concurrent Execution: Non-blocking assignments are scheduled to happen concurrently at the end of the current time step.
Delayed Update: The values on the right-hand side of all non-blocking assignments are evaluated first. Then, at the end of the time step, the values are assigned to the corresponding variables simultaneously.
Example :

reg a, b, c; 

always @ (posedge clk) begin
  a <= 1; 
  b <= a; 
  c <= b; 
end

In this example :

At the beginning of the time step, the right-hand sides of all assignments are evaluated.
- a is scheduled to be assigned 1.
- b is scheduled to be assigned the current value of a (which is its previous value).
- c is scheduled to be assigned the current value of b (which is its previous value).
At the end of the time step, all scheduled assignments are performed simultaneously.