What do you know about Verilog parallel and full case statements?
In Verilog, there are two different kinds of case statements.
Verilog parallel case statements : A statement that matches just one case item in a case expression is referred to as a parallel case statement. The matching case items are known as "overlapping case items," The case statement would not be parallel if you could find a case expression that would fit more than one case item.
Verilog full case statements : Every case expression in a Verilog full case statement must have binary patterns that match either a case item or the default. The case statement would not be regarded as complete if it did not include a case default and was likely to come across a binary case expression that did not match any of the specified case elements.
