What are the primary differences between Verilog's Task and Function?

Another most frequently asked Verilog interview question. The key distinctions between a Task and a Function in Verilog are as follows :

Task	Function
In Verilog, tasks can activate both additional tasks and functions.	A function in Verilog can enable other functions but cannot allow a task.
A task is permitted to contain any event, delay, or timing control statement.	Event, delay, or timing control statements are not allowed. Hence they cannot be contained in a function.
The simulation for tasks is also zero. However, they can also be carried out in a simulation time that is not zero if necessary.	Because the program time is not increased during the function routine, a function can do its required task in zero simulation time.
A task may employ zero or more arguments of the output or input types arguments.	A function must receive at least one parameter when it is invoked.
Using the output and input statements, a task can pass multiple values but cannot return a value.	Functions cannot employ either output or input statements and only return a single value.