What does a Verilog repeat loop do?

As its name suggests, the repeat loop behaves like loops used in popular programming languages like the for a loop. A repeat loop will execute a piece of code as often as it is accessed. The repeating piece of code will not make any reference to the loop cycle.

Syntax :
repeat(<no. of times the loop will run>) <statement to be repeated>?

Repetition in a line of code can be avoided with a repeat loop.