Explain the Verilog concepts of freeze, deposit, force, and drive.
It is important to know the various concepts of Verilog used as they are often asked in Verilog interview questions.
Freeze : For unresolved signals, use freeze. Throughout the simulation, the signal's value is frozen. You cannot modify this value.
Deposit : Deposit ensures that a signal value is kept until it is altered or replaced by the simulation. Throughout the simulation, it serves as value initialization.
Force : It can drive signals at any point during the simulation.
Drive : When the drive command gives a signal a value, it will "resolve" to a new value if the simulation updates the signal.
