In Verilog, what do the casex and casez statements mean?
Verilog has two different forms of case statements: casex and casez. All z values in the case alternatives or the case expression are treated as don't cares in this case by casez. The character? can also represent any bit position with the character z. All z and x values in the case item or the case expression are treated as don't cares by casex. We must use casex, and casez since do not cares are not permitted in a case statement.
