Correct Answer : Option (A) : All flip-flops are present with data.
Explanation : The actual meaning of the parallel load of a shift register is all flip-flops are present with data. It means that all of the register stages are loaded at a time with new data bits by a single load pulse. In the present condition, the outputs of flip flops will be 1. The value of Preset equals 1 means Q equals 1, this the value of the input is definitely 1.
